Europa!
RISC-V statt x86 und ARM: EU fördert Prozessorentwicklung
Das Projekt "Digital Autonomy with RISC-V in Europe" (DARE) vereint 38 Partnerfirmen und Forschungsinstitute, die Hochleitungs- und KI-Prozessoren entwickeln.
riscv
#StarPro64 EIC7700X is the Hot New #RISCV SBC by @PINE64 ... Let's boot Linux and Apache #NuttX RTOS ... Maybe run #LLM on NPU on NuttX? (Large Language Model + Neural Processing Unit)
I have managed to cross-compile mini-rv32ima (a tiny RISC-V Linux emulator) to 32-bit Windows and run it on Windows XP.
This is unbelievably cursed.
Current set of RISC-V boards ... From left to right - the first three are 32-bit, the others 64-bit. Most of these aren't used as much as they should be!
- SiFive HiFive1-A01 (Freedom E310)
- Base board for Doctor Who HiFive inventor kit (FE310-G002)
- Espressif ESP32-C3 microcontroller+LCD
- MangoPi D1 (Alibaba XuanTie C906) - The clear case it's in was for a Pi Zero
- HiFive Unleashed (Quad core Freedom U540)
- Beagle-V prototype (Dual core JH7100)
- VisionFive 2 (Quad core JH7110)
#riscv
Edited 1y ago
A recent PR by Logan Chien has added a RISC-V JIT backend to PyPy: https://github.com/pypy/pypy/pull/5002
This allows running PyPy with JIT on both emulated and physical RISC-V systems.
It's a great addition to PyPy and hopefully will attract the attention of RISC-V users and researchers to the project.
Wish there was a decent "kickstarter* / #groupbuy for getting one of the many truly libre #riscv cores made by a #fab. Ideally one that is as much "general purpose cpu" as possible, though I can certainly do without out of order, speculative, and all the other fancy common sources of cpu vulnerabilities. It doesn't need to win speed records, just being *really* rock-solid would be awesome *sigh*
